1. Field of the Invention
The present invention relates to a variable-length-code decoding device operable to decode bit streams encoded with a plurality of coding systems.
2. Description of the Related Art
The importance of the signal processing device in conformity with MPEG (Moving Picture Coding Experts Group) standards is increasing by the spread of transmission and reception of the digital image contents using digital satellite broadcasting service, the Internet, or portable information terminals. Currently, the MPEG standards include various coding systems, such as MPEG-1 for storage media, e.g. CD-ROM, MPEG-2 for digital TV broadcast and storage media, e.g. DVD, MPEG-4 for a moving picture format using low bit rates, used in, e.g. mobile communications, and MPEG-4 AVC (Advanced Video Coding) which was recently proposed with the aim of further high quality image communications at low bit rates.
When a mobile communication terminal operating on the premise of battery power adopts an MPEG system, it becomes a great concern that a vast quantity of data should be processed at high speed and power consumption therein should be reduced as well. From this viewpoint, a moving picture process-dedicated LSI installed in the mobile communication terminal uses together a processor and several pieces of dedicated hardware that process specific algorithms, such as a VLD (Variable Length Decoder), an IQ (Inverse Quantization) circuit, and an IDCT (Inverse Discrete Cosine Transform) circuit. In this way, the moving picture process-dedicated LSI distributes the load at the time of moving picture processing and reduces power consumption as well.
When the moving picture process-dedicated LSI is installed in an image processing device treating a plurality of coding systems and supports only one coding system, it is necessary to install in the image processing device a plurality of moving picture process-dedicated LSI's, each of which corresponds to each coding system.
However, if a plurality of moving picture process-dedicated LSI's is installed in the image processing device, the number of parts increases with accompanying increase in the cost of the image processing device, and the system will become complicated, since it is necessary to switch the plurality of moving picture process-dedicated LSI's to be operated for every coding system.
Therefore, it is possible to consider a device in which one moving picture process-dedicated LSI is made to treat the plurality of coding systems. Such a device may be realized by installing all necessary pieces of dedicated hardware such as VLD for every coding system. However, the device thus realized will result in increase of the area of the moving picture process-dedicated LSI, and hence in increase of the cost thereof.
Moreover, in order that one moving picture process-dedicated LSI is made to treat the plurality of coding systems, each dedicated hardware may be elaborately made to support each of the plurality of coding systems. As one of such resolutions, document 1 (Published Japanese patent application No. 2000-141807) discloses the art of the variable-length-code decoding circuit supporting two coding systems.
FIG. 7 shows the conventional variable-length-code decoding circuit 300 described by the document 1. The variable-length-code decoding circuit 300 comprises a barrel shifter 301, a barrel shifter controlling unit 302, a variable-length-code decoding table 303a for decoding of AC coefficients in a DV format and an MPEG format, a run length decoder 304 operable to process the run length of level 0, an escape processing circuit 303b dedicated for the MPEG format, a DC processing circuit 303c for each format, and an EOB processing circuit 303d for both formats.
When a bit stream of a DV format or an MPEG format is inputted, the processing circuit corresponding to each format calculates a run length and a level, and 0's are outputted as many as the number of the run length, thereby decoding the variable length code.
However, according to document 1, only two coding systems of DV and MPEG-1 or MPEG-2 can be supported. In order to support other coding systems, it is necessary to develop a circuit from the beginning according to a coding system to be supported, therefore, development man-hour increases. Furthermore, it is necessary to provide two kinds of tables etc. required for a variable length code decoding, one for DV and the other for MPEG-1 or MPEG-2. Therefore, compared with the case where it supports only one coding system, the circuit scale becomes larger and the cost of the moving picture process-dedicated LSI increases.
Therefore, the aim of the present invention is to provide a variable-length-code decoding device, which can support a plurality of coding systems easily, and suppress increase of the circuit scale.